1. Field
Exemplary embodiments of the present invention relate to a memory, and more particularly, to a self-refresh operation of a memory.
2. Description of the Related Art
A memory device receives diverse setup values and sets up operation timings in order to start an operation thereof after a power is supplied and then a certain time passes until the power supply is stabilized.
FIG. 1 illustrates an initialization process of a Double Data Rate 3 (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) device.
Referring to FIG. 1, a power supply voltage VDD and VDDQ is supplied, and a reset signal RESETB (which is a signal for resetting diverse circuits in a chip) is enabled to a logic low level to initialize the values of the various internal circuits, such as latch circuits, of a memory device. After such an initialization process is finished, i.e., at a ‘101’ moment, a clock enable signal CKE is enabled to a logic high level to start synchronous operations of the memory device and set various values MRS and MR based on the values applied as a command COMMAND and a bank address BA.
In FIG. 1, ‘CK’ denotes a clock, ‘CK#’ denotes an inverted clock, and ‘CKE’ denotes a clock enable signal, which is a signal indicating a period where a memory device is to operate in synchronization with a clock. Also, ‘MRS’ and ‘MR#’ indicate diverse setup values set up in the memory device. A part marked with oblique lines represents a “Don't Care” period. In FIG. 1, ‘tXPR’ denotes a reset CLE exit time; ‘tMRD’ denotes a cycle time of a mode register set (MRS) command; ‘tMOD’ denotes a delay time from an MRS command to a non-MRS command; and ‘tZQinit’ denotes an initial ZQ calibration time. The tXPR, tMRD, tMOD, and tZQinit may be parameters defined in a standard memory specification, i.e., Joint Electron Device Engineering Council (JEDEC) Specification.
Since the memory device does not perform any other operation therein during the initialization operation, the operations of the internal circuits in the memory device may not be stabilized. That is, when the power-up of a system using a memory device is relatively fast or a power supply voltage is undesirably instable, the internal circuits of the memory device may be instable at a booting, which may cause the operation of the memory device to malfunction.